Verilog HDL: 1-bit Full Adder Gate-level Circuit Description

This is a gate-level description of a 1-bit Full Adder. We use 2 Half Adder modules to return the Sum and Carry out of the inputs.

Structural Diagram Full Adder Module

 module FullAdder(A,B,Cin,Cout,S);  
      input A,B,Cin;  
      wire C1,C2,S1;  
      output Cout,S;  
        
      HalfAdder UUT1(.x(A), .y(B), .c(C1), .s(S1)); // S1 = (A)xor(B); C1 = (A)and(B);
      HalfAdder UUT2(.x(Cin), .y(S1), .c(C2), .s(S)); // S = (Cin)xor(S1); C2 = (Cin)and(S1);
      or G1(Cout,C1,C2); // Cout = (C1)or(C2);
        
 endmodule

Half Adder Module

 module HalfAdder(x,y,c,s);  
      input x,y;  
      output c,s;  
        
      xor G1(s,x,y); // s = (x) xor (y)
      and G2(c,x,y); // c = (x) and (y);
        
 endmodule  

Full Adder Testbench

 module tb_FullAdder;  
      reg A,B,Cin;  
      wire Cout,S;  
        
      FullAdder UUT(.A(A), .B(B), .Cin(Cin), .Cout(Cout), .S(S)); // Testing FullAdder Module
   
      initial begin  
           $dumpfile("FullAdder.vpd");  
           $dumpvars;  
             
           A=0; B=0; Cin=0; #10 // Testing all possible values...
           A=0; B=0; Cin=1; #10  
           A=0; B=1; Cin=0; #10  
           A=0; B=1; Cin=1; #10  
           A=1; B=0; Cin=0; #10  
           A=1; B=0; Cin=1; #10  
           A=1; B=1; Cin=0; #10  
           A=1; B=1; Cin=1; #10  
             
           $finish;  
      end  
 endmodule  

If you have any question, please, post a comment below.